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a microchip technology company ?2011 silicon storage technology, inc. ds25040a 05/11 data sheet www.microchip.com 16 mbit (x8) multi-purpose flash plus sst39vf1681 / sst39vf1682 features ? organized as 2m x8 ? single voltage read and write operations ? 2.7-3.6v ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 5 mhz) ? active current: 9 ma (typical) ? standby current: 3 a (typical) ? auto low power mode: 3 a (typical) ? hardware block-protection/wp# input pin ? top block-protection (top 64 kbyte) for sst39vf1682 ? bottom block-protection (bottom 64 kbyte) for sst39vf1681 ? sector-erase capability ? uniform 4 kbyte sectors ? block-erase capability ? uniform 64 kbyte blocks ? chip-erase capability ? erase-suspend/erase-resume capabilities ? hardware reset pin (rst#) ? security-id feature ? sst: 128 bits; user: 128 bits ? fast read access time: ?70ns ? latched address and data ? fast erase and byte-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? byte-program time: 7 s (typical) ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bits ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 48-ball tfbga (6mm x 8mm) ? 48-lead tsop (12mm x 20mm) ? all devices are rohs compliant the sst39vf1681 / sst39vf1682 are 2m x8 cmos multi-purpose flash plus (mpf+) manufactured with sst proprietary, high performance cmos super- flash? technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39vf1681 / sst39vf1682 write (program or erase) with a 2.7-3.6v power supply. these devices conforms to jedec standard pinouts for x8 memo- ries.
?2011 silicon storage technology, inc. ds25040a 05/11 2 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company product description the sst39vf168x devices are 2m x8 cmos multi-purpose flash plus (mpf+) manufactured with sst?s proprietary, high performance cmos superflash? technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39vf168x write (program or erase) with a 2.7-3.6v power supply. these devices conform to jedec standard pinouts for x8 memories. featuring high performance byte-program, the sst39vf168x devices provide a typical byte-program time of 7 sec. these devices use toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent write, they have on-chip hardware and software data protec- tion schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39vf168x devices are suited for applications that require convenient and economical updat- ing of program, configuration, or data memory. for all system applications, they significantly improve performance and reliability, while lowering power consumption. they inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed dur- ing any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and pro- gram times increase with accumulated erase/program cycles. to meet high density, surface mount requirements, the sst39vf168x are offered in both 48-ball tfbga and 48-lead tsop packages. see figures 2 and 3 for pin assignments.
?2011 silicon storage technology, inc. ds25040a 05/11 3 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company block diagram figure 1: sst39vf1681 / sst39vf1682 block diagram pin description figure 2: pin assignments for 48-lead tfbga y-decoder i/o buffers and data latches 1243 b1.0 address buffer latches x-decoder dq 7 -dq 0 memory address oe# ce# we# superflash memory control logic wp# reset# 1243 48-tfbga b3k p1.0 top view (balls facing down) 6 5 4 3 2 1 a14 a10 we# nc a8 a4 a13 a9 rst# wp# a18 a5 a15 a11 nc a19 a7 a3 a16 a12 a20 nc a6 a2 a17 dq7 dq5 dq2 dq0 a1 nc nc nc nc nc ce# a0 nc v dd nc nc oe# v ss dq6 dq4 dq3 dq1 v ss abcdefgh
?2011 silicon storage technology, inc. ds25040a 05/11 4 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 3: pin assignments for 48-lead tsop table 1: pin description symbol pin name functions a ms 1 -a 0 1. a ms = most significant address a ms =a 20 for sst39vf1681/1682 address inputs to provide memory addresses. during sector-erase a ms -a 12 address lines will select the sector. during block-erase a ms -a 16 address lines will select the block. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. wp# write protect to protect the top/bottom boot block from erase/program operation when grounded. rst# reset to reset and return the device to read mode. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 2.7-3.6v v ss ground nc no connection unconnected pins. t1.1 25040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a17 nc v ss a0 dq7 nc dq6 nc dq5 nc dq4 v dd nc dq3 nc dq2 nc dq1 nc dq0 oe# v ss ce# a1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1243 48-tsop p2.0 standard pinout to p v i e w die up a16 a15 a14 a13 a12 a11 a10 a9 a20 nc we# rst# nc wp# nc a19 a18 a8 a7 a6 a5 a4 a3 a2
?2011 silicon storage technology, inc. ds25040a 05/11 5 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst39vf168x also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read cur- rent from typically 9 ma to typically 3 a. the auto low power mode reduces the typical i dd active read current to the range of 2 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto-low power mode after power-up with ce# held steadily low, until the first address transition or ce# is driven high. read the read operation of the sst39vf168x is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle tim- ing diagram for further details (figure 4). byte-program operation the sst39vf168x are programmed on a byte-by-byte basis. before programming, the sector where the byte exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. during the byte-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initi- ated, will be completed within 10 s. see figures 5 and 6 for we# and ce# controlled program opera- tion timing diagrams and figure 20 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. during the command sequence, wp# should be statically held high or low. sector/block-erase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. the sst39vf168x offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 4 kbyte. the block-erase mode is based on uniform block size of 64 kbyte. the sector-erase operation is initiated by executing a six-byte command sequence with sector-erase command (50h) and sector address (sa) in the last bus cycle. the block- erase operation is initiated by executing a six-byte command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase opera- tion can be determined using either data# polling or toggle bit methods. see figures 10 and 11 for
?2011 silicon storage technology, inc. ds25040a 05/11 6 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company timing waveforms and figure 24 for the flowchart. any commands issued during the sector- or block- erase operation are ignored. when wp# is low, any attempt to sector- (block-) erase the protected block will be ignored. during the command sequence, wp# should be statically held high or low. erase-suspend/erase-resume commands the erase-suspend operation temporarily suspends a sector- or block-erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an erase operation. the operation is executed by issuing one byte command sequence with erase- suspend command (b0h). the device automatically enters read mode typically within 20 s after the erase-suspend command had been issued. valid data can be read from any sector or block that is not suspended from an erase operation. reading at address location within erase-suspended sectors/ blocks will output dq 2 toggling and dq 6 at ?1?. while in erase-suspend mode, a byte-program opera- tion is allowed except for the sector or block selected for erase-suspend. to resume sector-erase or block-erase operation which has been suspended the system must issue erase resume command. the operation is executed by issuing one byte command sequence with erase resume com- mand (30h) at any address in the last byte sequence. chip-erase operation the sst39vf168x provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six-byte command sequence with chip-erase command (10h) at address aaah in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# poll- ing. see table 6 for the command sequence, figure 10 for timing diagram, and figure 24 for the flowchart. any commands issued during the chip-erase operation are ignored. when wp# is low, any attempt to chip- erase will be ignored. during the command sequence, wp# should be statically held high or low. write operation status detection the sst39vf168x provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two sta- tus bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the sys- tem may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 .in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has com- pleted the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the sst39vf168x are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent succes- sive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will pro-
?2011 silicon storage technology, inc. ds25040a 05/11 7 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company duce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for data# polling tim- ing diagram and figure 21 for a flowchart. toggle bits (dq6 and dq2) during the internal program or erase operation, any consecutive attempts to read dq 6 will produce alternating ?1?s and ?0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next operation. for sector- , block-, or chip-erase, the toggle bit (dq 6 ) is valid after the rising edge of sixth we# (or ce#) pulse. dq 6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if pro- gram operation is initiated in a sector/block not selected in erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq 2 , which can be used in conjunction with dq 6 to check whether a particular sector is being actively erased or erase-suspended. table 2 shows detailed status bits information. the toggle bit (dq 2 ) is valid after the rising edge of the last we# (or ce#) pulse of write operation. see figure 8 for toggle bit timing diagram and figure 21 for a flowchart. note: dq 7 and dq 2 require a valid address when reading status information. data protection the sst39vf168x provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd p o w er up/do wn detection: the write operation is inhibited when v dd is less than 1.5v. wr ite inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this pre- vents inadvertent writes during power-up or power-down. table 2: write operation status status dq 7 dq 6 dq 2 normal operation standard program dq 7 # toggle no toggle standard erase 0 toggle toggle erase-suspend mode read from erase suspended sector/block 1 1 toggle read from non- erase suspended sector/block data data data program dq 7 # toggle n/a t2.0 25040
?2011 silicon storage technology, inc. ds25040a 05/11 8 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company hardware block protection the sst39vf1682 supports top hardware block protection, which protects the top 64 kbyte block of the device. the sst39vf1681 supports bottom hardware block protection, which protects the bottom 64 kbyte block of the device. the boot block address ranges are described in table 3. program and erase operations are prevented on the 64 kbyte when wp# is low. if wp# is left floating, it is internally held high via a pull-up resistor, and the boot block is unprotected, enabling program and erase opera- tions on that block. hardware reset (rst#) the rst# pin provides a hardware method of resetting the device to read array data. when the rst# pin is held low for at least t rp, any in-progress operation will terminate and return to read mode. when no internal program/erase operation is in progress, a minimum period of t rhr is required after rst# is driven high before a valid read can take place (see figure 16). the erase or program operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. software data protection (sdp) the sst39vf168x provide the jedec approved software data protection scheme for all data altera- tion operations, i.e., program and erase. any program operation requires the inclusion of the three- byte sequence. the three-byte load sequence is used to initiate the program operation, providing opti- mal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. these devices are shipped with the software data protection permanently enabled. see table 6 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc. common flash memory interface (cfi) the sst39vf168x also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as product id entry command with 98h (cfi query command) to address aaah in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 7 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode. table 3: boot block address ranges product address range bottom boot block sst39vf1681 000000h-00ffffh top boot block sst39vf1682 1f0000h-1fffffh t3.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 9 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company product identification the product identification mode identifies the devices as the sst39vf1681 and sst39vf1682, and manu- facturer as sst. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 6 for software operation, figure 12 for the software id entry and read timing diagram, and figure 22 for the software id entry command sequence flowchart. product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accomplished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inad- vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor- rectly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see t able 6 for software command codes, figure 14 for timing waveform, and figures 22 and 23 for flowcharts. security id the sst39vf168x devices offer a 256-bit security id space which is divided into two 128-bit seg- ments. the first segment is programmed and locked at sst with a random 128-bit number. the user segment is left un-programmed for the customer to program as desired. to program the user segment of the security id, the user must use the security id byte-program com- mand. to detect end-of-write for the sec id, read the toggle bits. do not use data# polling. once this is complete, the sec id should be locked using the user sec id program lock-out. this disables any future corruption of this space. note that regardless of whether or not the sec id is locked, neither sec id segment can be erased. the security id space can be queried by executing a three-byte command sequence with enter-sec- id command (88h) at address aaah in the last byte sequence. execute the exit-sec-id command to exit this mode. refer to t able 6 for more details. table 4: product identification address data manufacturer?s id 0000h bfh device id sst39vf1681 0001h c8h sst39vf1682 0001h c9h t4.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 10 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company operations table 5: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 6 t5.0 25040 table 6: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 11 -a 0 (hex). addresses a 20 -a 12 can be v il or v ih , but no other value, for command sequence for sst39vf1681/1682. data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program aaah aah 555h 55h aaah a0h ba 2 2. ba = program byte address data sector-erase aaah aah 555h 55h aaah 80h aaah aah 555h 55h sa x 3 3. sa x for sector-erase; uses a ms -a 12 address lines ba x , for block-erase; uses a ms -a 16 address lines a ms = most significant address a ms =a 20 for sst39vf1681/1682 50h block-erase aaah aah 555h 55h aaah 80h aaah aah 555h 55h ba x 3 30h chip-erase aaah aah 555h 55h aaah 80h aaah aah 555h 55h aaah 10h erase-suspend xxxxh b0h erase-resume xxxxh 30h query sec id 4 aaah aah 555h 55h aaah 88h user security id byte-program aaah aah 555h 55h aaah a5h ba 5 data user security id program lock-out aaah aah 555h 55h aaah 85h xxh 5 00h software id entry 6,7 aaah aah 555h 55h aaah 90h cfi query entry aaah aah 555h 55h aaah 98h software id exit 8,9 /cfi exit/sec id exit aaah aah 555h 55h aaah f0h software id exit 8,9 /cfi exit/sec id exit xxh f0h t6.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 11 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company 4. with a ms -a 5 = 0; sec id is read with a 4 -a 0 , sst id is read with a 4 = 0 (address range = 00000h to 0000fh), user id is read with a 4 = 1 (address range = 00010h to 0001fh). lock status is read with a 7 -a 0 = 0000ffh. unlocked: dq 3 = 1 / locked: dq 3 =0. 5. valid byte addresses for sec id are from 000000h-00000fh and 000020h-00002fh. 6. the device does not remain in software product id mode if powered down. 7. with a ms -a 1 =0; sst manufacturer id = 00bfh, is read with a 0 =0, sst39vf1681 device id = c8h, is read with a 0 =1, sst39vf1682 device id = c9h, is read with a 0 =1, a ms = most significant address a ms =a 20 for sst39vf1681/1682 8. both software id exit operations are equivalent 9. if users never lock after programming, sec id can be programmed over the previously unprogrammed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). table 7: cfi query identification string 1 1. refer to cfi publication 100 for more details. address data data 10h 51h query unique ascii string ?qry? 11h 52h 12h 59h 13h 01h primary oem command set 14h 07h 15h 00h address for primary extended table 16h 00h 17h 00h alternate oem command set (00h = none exists) 18h 00h 19h 00h address for alternate oem extended table (00h = none exits) 1ah 00h t7.1 25040 table 8: system interface information address data data 1bh 27h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 36h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 00h v pp min. (00h = no v pp pin) 1eh 00h v pp max. (00h = no v pp pin) 1fh 03h typical time out for byte-program 2 n s (2 3 = 8 s) 20h 00h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 04h typical time out for individual sector/block-erase 2 n ms (2 4 =16ms) 22h 05h typical time out for chip-erase 2 n ms (2 5 =32ms) 23h 01h maximum time out for byte-program 2 n times typical (2 1 x2 3 =16s) 24h 00h maximum time out for buffer program 2 n times typical 25h 01h maximum time out for individual sector/block-erase 2 n times typical (2 1 x2 4 =32ms) 26h 01h maximum time out for chip-erase 2 n times typical (2 1 x2 5 =64ms) t8.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 12 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company table 9: device geometry information address data data 27h 15h device size = 2 n bytes (15h = 21; 2 21 = 2 mbyte) 28h 00h flash device interface description; 00h = x8-only asynchronous interface 29h 00h 2ah 00h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 00h 2ch 02h number of erase sector/block sizes supported by device 2dh ffh sector information ( y+1= number of sectors; z x 256b = sector size) 2eh 01h y=511+1=512 sectors (01ff = 511 2fh 10h 30h 00h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 1fh block information ( y+1= number of blocks; z x 256b = block size) 32h 00h y=31+1=32blocks(1f=31) 33h 00h 34h 01h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t9.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 13 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias ............................................. -55c to +125c storage temperature ................................................ -65c to +150c d. c. voltage on any pin to ground potential ............................ -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential .................. -2.0v to v dd +2.0v voltage on a 9 pin to ground potential ..................................... -0.5v to 13.2v package power dissipation capability (ta = 25c) .................................. 1.0w surface mount lead soldering temperature (3 seconds) ............................ 240c output short circuit current 1 .................................................. 50ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. table 10: operating range range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v t10.1 25040 table 11: ac conditions of test 1 1. see figures 18 and 19 input rise/fall time output load 5ns c l =30pf t11.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 14 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company table 12: dc operating characteristics v dd = 2.7-3.6v 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht 2 , at f=5 mhz, v dd =v dd max read 3 18 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 35 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#=v ihc ,v dd =v dd max i alp auto low power 20 a ce#=v ilc ,v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd ,v dd =v dd max i liw input leakage current on wp# pin and rst# 10 a wp#=gnd to v dd or rst#=gnd to v dd i lo output leakage current 10 a v out =gnd to v dd ,v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t12.8 25040 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 3v. not 100% tested. 2. see figure 18 3. the i dd current listed is typically less than 2ma/mhz, with oe# at v ih. typical v dd is 3v. table 13: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t13.0 25040 table 14: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. i/o pin capacitance v i/o =0v 12pf c in 1 input capacitance v in =0v 6pf t14.0 25040
?2011 silicon storage technology, inc. ds25040a 05/11 15 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company ac characteristics table 15: reliability characteristics symbol parameter minimum specification units test method n end 1,2 endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 t15.2 25040 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. n end endurance rating is qualified as a 10,000 cycle minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. table 16: read cycle timing parameters v dd = 2.7-3.6v symbol parameter sst39vf168x-70 units min max t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t rp 1 rst# pulse width 500 ns t rhr 1 rst# high before read 50 ns t ry 1,2 2. this parameter applies to sector-erase, block-erase, and program operations. this parameter does not apply to chip-erase operations. rst# pin low to read mode 20 s t16.1 25040
?2011 silicon storage technology, inc. ds25040a 05/11 16 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company table 17: program/erase cycle timing parameters symbol parameter min max units t bp byte-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t17.0 25040 1. this parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
?2011 silicon storage technology, inc. ds25040a 05/11 17 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 4: read cycle timing diagram figure 5: we# controlled program cycle timing diagram 1243 f02.0 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms =a 20 for sst39vf168x 1243 f03.2 address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 aaa aaa 555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp note: a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25040a 05/11 18 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 6: ce# controlled program cycle timing diagram figure 7: data# polling timing diagram 1243 f04.2 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 aaa aaa 555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp note: a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1243 f05.1 address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms =a 20 for sst39vf168x
?2011 silicon storage technology, inc. ds25040a 05/11 19 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 8: toggle bits timing diagram figure 9: we# controlled chip-erase timing diagram 1243 f06.1 address a ms-0 dq 6 and dq 2 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms =a 20 for sst39vf168x 1243 f07.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 aaa aaa aaa 555 aaa 55 10 55 aa 80 aa 555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are meet. (see table 17.) a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25040a 05/11 20 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 10: we# controlled block-erase timing diagram 1243 f08.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 55 30 55 aa 80 aa ba x oe# ce# six-byte code for block-erase t be t wp aaa aaa 555 aaa 555 note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are meet. (see table 17.) ba x = block address a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25040a 05/11 21 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 11: we# controlled sector-erase timing diagram 1243 f9.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 55 50 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp aaa aaa 555 aaa 555 note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are meet. (see table 17.) sa x = sector address a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25040a 05/11 22 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 12: software id entry and read figure 13: cfi query entry and read 1243 f10.1 address a ms-0 t ida dq 7-0 we# sw0 sw1 sw2 aaa aaa 555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90 note: device id - see table 4 on page 9 a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1243 f11.2 address a ms-0 t ida dq 7-0 we# sw0 sw1 sw2 555 aaa aaa oe# ce# three-byte sequence for cfi query entry t wp t wph t aa 55 aa 98 note: a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25040a 05/11 23 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 14: software id exit/cfi exit figure 15: sec id entry 1243 f12.2 address a ms-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 aaa aaa 555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0 note: a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value. 1243 f13.1 address a ms-0 t ida dq 7-0 we# sw0 sw1 sw2 aaa aaa 555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa 55 aa 88 note: a ms = most significant address a ms =a 20 for sst39vf168x wp# must be held in proper logic state (v il or v ih ) 1 s prior to and 1 s after the command sequence. x can be v il or v ih, but no other value.
?2011 silicon storage technology, inc. ds25040a 05/11 24 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 16: rst# timing diagram (when no internal operation is in progress) figure 17: rst# timing diagram (during program or erase operation) 1243 f14.0 rst# ce#/oe# t rp t rhr 1243 f15.0 rst# ce#/oe# t rp t ry end-of-write detection (toggle-bit)
?2011 silicon storage technology, inc. ds25040a 05/11 25 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 18: ac input/output reference waveforms figure 19: a test load example 1243 f16.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. mea- surement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it -v input test v ot -v output test v iht -v input high test v ilt -v input low test 1243 f17.0 to tester to dut c l
?2011 silicon storage technology, inc. ds25040a 05/11 26 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 20: byte-program algorithm 1243 f18.0 start load data: aah address: aaah load data: 55h address: 555h load data: a0h address: aaah load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih , but no other value
?2011 silicon storage technology, inc. ds25040a 05/11 27 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 21: wait options 1243 f19.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data read dq 7 program/erase initiated program/erase initiated
?2011 silicon storage technology, inc. ds25040a 05/11 28 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 22: software id/cfi entry command flowcharts 1243 f20.0 load data: aah address: aaah software product id entry command sequence load data: 55h address: 555h load data: 90h address: 5555h wait t ida read software id load data: aah address: aaah cfi query entry command sequence load data: 55h address: 555h load data: 98h address: aaah wait t ida read cfi data load data: aah address: aaah sec id query entry command sequence load data: 55h address: 555h load data: 88h address: aaah wait t ida read sec id x can be v il or v ih , but no other value
?2011 silicon storage technology, inc. ds25040a 05/11 29 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 23: software id/cfi exit command flowcharts 1243 f21.0 load data: aah address: aaah software id exit/cfi exit/sec id exit command sequence load data: 55h address: 555h load data: f0h address: aaah load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih, but no other value
?2011 silicon storage technology, inc. ds25040a 05/11 30 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 24: erase command sequence 1243 f22.0 load data: aah address: aaah chip-erase command sequence load data: 55h address: 555h load data: 80h address: aaah load data: 55h address: 555h load data: 10h address: aaah load data: aah address: aaah wait t sce chip erased to ffffh load data: aah address: aaah sector-erase command sequence load data: 55h address: 555h load data: 80h address: aaah load data: 55h address: 555h load data: 50h address: sa x load data: aah address: aaah wait t se sector erased to ffffh load data: aah address: aaah block-erase command sequence load data: 55h address: 555h load data: 80h address: aaah load data: 55h address: 555h load data: 30h address: ba x load data: aah address: aaah wait t be block erased to ffffh x can be v il or v ih , but no other value
?2011 silicon storage technology, inc. ds25040a 05/11 31 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company product ordering information valid combinations for sst39vf1681 sst39vf1681-70-4c-eke sst39vf1681-70-4c-b3ke sst39vf1681-70-4i-eke sst39vf1681-70-4i-b3ke valid combinations for sst39vf1682 sst39vf1682-70-4c-eke sst39vf1682-70-4c-b3ke sst39vf1682-70-4i-eke sst39vf1682-70-4i-b3ke note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. sst 39 vf 1681 - 70 - 4c - b3ke xx xx xxxx - xx - xx - xxxx environmental attribute e 1 = non-pb package modifier k = 48 leads package type b3 = tfbga (6mm x 8mm, 0.8mm pitch) e = tsop (type1, die up, 12mm x 20mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70=70ns hardware block protection 1 = bottom boot-block 2 = top boot-block device density 168 = 16 mbit voltage v = 2.7-3.6v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?.
?2011 silicon storage technology, inc. ds25040a 05/11 32 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company packaging diagrams figure 25: 48-lead thin small outline package (tsop) 12mm x 20mm sst package code: ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0- 5 detail pin # 1 identifier 0.50 bsc
?2011 silicon storage technology, inc. ds25040a 05/11 33 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company figure 26: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k a1 corner hgfedcba abcdefgh bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.10 0.45 0.05 (48x) a1 corner 8.00 0.10 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-5 note: 1. complies with jedec publication 95, mo-210, variant ab-1 , although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm
?2011 silicon storage technology, inc. ds25040a 05/11 34 16 mbit multi-purpose flash plus sst39vf1681 / sst39vf1682 data sheet a microchip technology company table 18: revision history number description date 00 ? initial release may 2003 01 ? change product number from 166x to 168x sep 2003 02 ? added b3k package and associated mpns (see page 31) ? removed 90 ns commercial temperature for the ek and eke packages oct 2003 03 ? 2004 data book ? updated b3k package diagram nov 2003 a ? updated document status to ?data sheet.? ? removed all 90ns information. edited ?features? on page 1, ?product ordering information? on page 31, and table 16 on page 15. ? updated t ida information in table 17 on page 16 ? applied new document format ? released document under the letter revision system ? updated spec number from s71243 to ds25040 may 2011 ? 2011 silicon storage technology, inc?a microchip technology company. all rights reserved. sst, silicon storage technology, the sst logo, superflash, mtp, and flashflex are registered trademarks of silicon storage tech- nology, inc. mpf, sqi, serial quad i/o, and z-scale are trademarks of silicon storage technology, inc. all other trademarks and registered trademarks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for the most recent documentation. for the most current package drawings, please see the packaging specification located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity; actual usable capacity may be less. sst makes no warranty for the use of its products other than those expressly contained in the standard terms and conditions of sale. for sales office(s) location and information, please see www.microchip.com. silicon storage technology, inc. a microchip technology company www.microchip.com isbn:978-1-61341-202-2

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